In  integrated  circuit  (IC)  technology,  decades  of  progress  were  driven  by  the  continued  miniaturization of transistor dimensions to yield greater circuit density and functionality at lower cost and power per function. Currently, however, the chip industry is facing a crisis. Although transistor scaling has provided for enhanced performance, it has also resulted in increased  in  power  per  unit  area  of  a  chip.  This  is  manifested  in  today’s  typical  Complementary Metal-­Oxide-­Semiconductor (CMOS) processor, which operates at around the  power  density  of  a  nuclear  reactor.  The  fundamental  reason  for  the  rapid  rise  in  the  power density is that the supply voltage (VDD) used to drive the transistors has not scaled respectively  with  transistor  density.  Simply,  transistor  dimensions  have  continued  to  shrink  to  minute  scales,  but  the  voltage  used  to  operate  these  transistors  has  plateaued. Since the MOSFET is not an ideal switch, the off-­state leakage current (IOFF) is non-­zero and hence dissipates power even when it is supposed to be off. In 2011, Intel’s 22 nm CMOS node is the 1st commercially available bulk-FinFET technology and opens a new era of 3D CMOS  for  low  power  mobile  electronics  and  continuously  driving  CMOS  scaling  and  Moore’s Law. However, at 10 nm node and beyond, new design requirements are essential for switching capabilities of FinFET for optimal energy efficiency. This allocation supports a new solution in design enablement by using the power of computational simulations and high  performance  computing  clusters  for  cost  effective  and  energy  efficient  switches  for  FinFET device technology.