Processor resource needs vary across applications as well as within individual applications.  Some programs may be memory intensive; others may have a high amount of branching, while others may need many floating point computations.  Maximal configurations waste power when an application’s performance would not be degraded running on a lower power configuration.  By adjusting a processor’s configuration during application runtime, it is possible to save power without a performance cost.
      However, maximizing performance and minimizing power are two conflicting objectives.  Knowing what configuration will be best at a given time for a running program is not easily determined.  Adjusting a small number of microarchitectural parameters at a time can detract from the overall performance/power achievements that can be attained by adjusting a large number of parameters all together.  Additionally, processor variability affects the model’s effectiveness.  This framework allows for building separate loadable models for chips with different leakage percentages.
      A machine learning technique is used to determine optimal configurations during program execution.  Specifically ‘support vector regression’ (SVR) is used to determine the best configurations for a given power level which maximizes performance in terms of IPC while constraining power to some user defined level.  This framework reduces power in a global manner by determining optimal configurations for more than 17 variable microarchitectural parameters simultaneously in order to benefit from any interaction these units may have on each other.  This number of variables makes it impossible to try every combination of all parameters in a trial and error method; therefore a machine learning approach was chosen to attack this problem.
      A framework is provided for determining unified optimal power/performance configurations for adaptive processors at runtime. This framework has the advantage of being adaptable post silicon, compensating for the inevitable variability in leakage and transistor characteristics.