Dataflow Software Pipelining for Codelet Model Using Hardware-Software Co-Design

Siddhisanket (Sid) Raskar, University of Delaware
2020 Performance, Portability, and Productivity in HPC Forum

Software pipelining is a code mapping scheme to exploit pipelined parallelism in a loop. It has been successfully applied by compilers to exploit Instruction Level Parallelism(ILP) in a loop body, capable of scheduling up to a couple hundreds of machine instructions in pipelined execution. However, rapid advances in chip technology and computer architecture have enabled the design and production of chips with thousands of cores - far beyond the limit of ILP. Can the software pipeline technology be extended and applied to meet such challenges? 

This work addresses the above challenges by extending the software pipeline technology beyond the limit of fine-grain(ILP) level parallelism. We propose that this can be accomplished through dataflow software pipelining technology and its extension to the Codelet-based program execution model with dataflow origin.  

We show promising improvements when using the Extended Codelet Model with Dataflow Software Pipelining compared to the base Codelet model.


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