The Bit-Nibble-Byte MicroEngine (BnB) for Efficient Computing on Short Data Format

Dilip Vasudevan
Seminar

CT

Argonne National Laboratory
Building 240/Room 4301
Event Sponsor Argonne Leadership Computing Facility Seminar

This seminar presents an insight in to the federated heterogeneous computer architecture design called “10x10 Architecture”. A glimpse on the design of one of the microengines/ accelerators of the 10x10 architecture called BnB (Bit-Nibble-Byte) will be presented. With the BnB microengine design, audience will be guided through the overall flow of 10x10 system design process highlighting the benefits of this systematic approach for federated heterogeneity.

Energy is a critical challenge in computing performance. Due to the “word size creep” from modern CPUs, they are inefficient for short-data element processing. Many applications such as 2D convolution, Discrete Wavelet Transform (DWT), Advanced Encryption Standard (AES), Data compression and Galois Field (GF) Operations require short fixed point or bit-level manipulations, but such operations are often not well supported on modern architectures.

Most of these algorithms are composed of several sub-functions, which compute low-level bit operations like shifting, rotation, shuffling and logical operations. In traditional RISC ISA’s, even extended by multimedia extensions, these operations incur high instruction count, runtime, and energy overheads. This challenge motivates us to implement efficient bit level operations supporting several data sizes and better instructions and intrinsics to carry out these operations.

We propose and evaluate a new microarchitecture called “Bit-Nibble-Byte” (BnB). We evaluate the BnB Design mapped into 32nm and 7nm transistor technologies, and in combination with a variety of memory systems (DDR3 and HMC). The evaluation is based on both handwritten and compiled code with a custom compiler built for BnB. Our results include significant performance (19-252x) and energy benefits (5.6-140.7x) for short bit-field operations typically assumed to require hardwired accelerators and large-scale applications with compiled code.

A clear insight in to the practical design process of the systematic approach for the federated heterogeneous computer architecture will also be a takeaway from this seminar.