Pixel detectors are critical components driving advancements in scientific discovery across various fields. From enabling high-resolution X-ray crystallography to achieving atomic resolution

in cryo-electron microscopy, these technologies have revolutionized biochemistry. Next-generation light sources, offering 100 to 1,000 times greater X-ray beam brightness and coherent flux, demand pixel detectors capable of continuous frame rates approaching 1 MHz. However, these advancements pose significant challenges: even a modest detector operating at 1 MHz would require 1 Tbps bandwidth, creating a critical bottleneck for off-chip data transfer. In this talk, I will explore technology choices for achieving efficient streaming computation for X-ray detectors, including on- hip accelerators, chiplet-based architectures, and near-detector AI accelerators. On-chip accelerators provide unparalleled efficiency but require labor-intensive register-transfer level design. Chiplet-based solutions decouple sensing and computing, enabling modularity, while integrating AI accelerators simplifies programming but introduces challenges in establishing seamless connections between detectors and accelerators. To fully unlock the potential of next-generation experiments, we must reimagine data processing at the sensor level. Understanding and leveraging different architectural technologies and approaches is essential to meeting these demands effectively.

Bio: Kazutomo Yoshii is a Principal Experimental Systems Specialist at Argonne National Laboratory. He earned an M.S. in Computer Science from Toyohashi University of Technology, Japan, in 1994. His career began at Hitachi’s research facility in Japan, where he developed medical imaging analysis software for functional MRI data. In 1998, he joined Turbolinux, contributing to the Linux operating system in both Japan and Santa Fe, New Mexico. In 2002, he transitioned to Mountain View Data, focusing on dynamic provisioning systems for cluster environments. Since December 2004, he has been with Argonne, actively engaging in co-design activities for supercomputers and scientific

experimental systems. His recent work focuses on custom accelerator designs and streaming near-sensor processing architectures. His research interests include high-performance computing, power-aware computing, reconfigurable dataflow computing, hardware development tools, and hardware specialization.

See all upcoming talks at https://www.anl.gov/mcs/lans-seminars